1 file number 2307.3 caution: these devices are sensitive to electrostatic discharge; follow proper esd handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 irf340 10a, 400v, 0.550 ohm, n-channel power mosfet this n-channel enhancement mode silicon gate power ?eld effect transistor is designed, tested and guaranteed to withstand a speci?c level of energy in the breakdown avalanche mode of operation. these mosfets are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. these types can be operated directly from integrated circuits. formerly developmental type ta17424. features ? 10a, 400v ?r ds(on) = 0.550 w ? single pulse avalanche energy rated ? soa is power-dissipation limited ? nanosecond switching speeds ? linear transfer characteristics ? high input impedance ? majority carrier device ? related literature - tb334 guidelines for soldering surface mount components to pc boards symbol packaging jedec to-204ae ordering information part number package brand irf340 to-204ae irf340 note: when ordering, use the entire part number. d g s drain (flange) source (pin 2) gate (pin 1) data sheet march 1999
2 absolute maximum ratings t c = 25 o c, unless otherwise speci?ed irf340 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ds 400 v drain to gate voltage (r gs = 20k w) (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v dgr 400 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i d t c = 100 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i d 10 6.3 a a pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 40 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d 125 w linear derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 w/ o c single pulse avalanche energy rating (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as 520 mj operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j, t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t pkg 300 260 o c o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. t j = 25 o c to 125 o c. electrical speci?cations t c = 25 o c, unless otherwise speci?ed parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 m a, v gs = 0v (figure 10) 400 - - v gate threshold voltage v gs(th) v ds = v gs , i d = 250 m a 2.0 - 4.0 v zero gate voltage drain current i dss v ds = rated bv dss , v gs = 0v - - 25 m a v ds = 0.8 x rated bv dss , v gs = 0v, t j = 150 o c - - 250 m a on-state drain current (note 2) i d(on) v ds > i d(on) x r ds(on)max , v gs = 10v 10 - - a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance (note 2) r ds(on) i d = 5.2a, v gs = 10v (figures 8, 9) - 0.4 0.550 w forward transconductance (note 2) g fs v ds 3 50v, i d = 5.2a (figure 12) 5.8 8 - s turn-on delay time d(on) v dd = 200v, i d ? 10a, r g = 9.1 w , r l = 19.5 w (figures 17, 18) mosfet switching times are essentially independent of operating temperature -1721ns rise time t r -2741ns turn-off delay time t d(off) -4575ns fall time t f -2036ns total gate charge (gate to source + gate to drain) q g(tot) v gs = 10v, i d = 10a, v ds = 0.8 x rated bv dss i g(ref) = 1.5ma (figures 14, 19, 20) gate charge is essentially independent of operating temperature -4163nc gate to source charge q gs -7-nc gate to drain miller charge q gd -23- nc input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 11) - 1250 - pf output capacitance c oss - 300 - pf reverse transfer capacitance c rss -80- pf internal drain inductance l d measured between the contact screw on header that is closer to source and gate pins and center of die modified mosfet symbol showing the internal device inductances - 5.0 - nh internal source inductance l s measured from the source lead, 6mm (0.25in) from header and source bonding pad - 12.5 - nh thermal resistance junction to case r q jc - - 1.0 o c/w thermal resistance junction to ambient r q ja free air operation - - 30 o c/w l s l d g d s irf340
3 source to drain diode speci?cations parameter symbol test conditions min typ max units continuous source to drain current i sd modified mosfet symbol showing the integral reverse p-n junction rectifier - - 10 a pulse source to drain current (note 3) i sdm - - 40 a drain to source diode voltage (note 2) v sd t j = 25 o c, i sd = 9.2a, v gs = 0v (figure 13) - - 2.0 v reverse recovery time t rr t j = 25 o c, i sd = 9.2a, di sd /dt = 100a/ m s 170 350 790 ns reverse recovery charge q rr t j = 25 o c, i sd = 9.2a, di sd /dt = 100a/ m s 1.6 4.0 8.2 m c notes: 2. pulse test: pulse width 300 m s, duty cycle 2%. 3. repetitive rating: pulse width limited by max junction temperature. see transient thermal impedance curve (figure 3). 4. v dd = 50v, starting t j = 25 o c, l = 9.2mh, r g = 25 w , peak i as = 10a (figures 15, 16). typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance g d s 0 50 100 150 0 t c , case temperature ( o c) power dissipation multiplier 0.2 0.4 0.6 0.8 1.0 1.2 25 50 75 100 125 150 10 8 6 4 2 0 t c , case temperature ( o c) i d , drain current (a) 10 -5 10 -4 10 -3 10 -2 0.1 1 10 1 0.1 0.01 10 -3 z q jc, transient thermal impedance t 1 , rectangular pulse duration (s) 0.5 0.2 0.1 0.05 0.02 0.01 single pulse p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z q jc + t c 2 irf340
4 figure 4. forward bias safe operating area figure 5. output characteristics figure 6. saturation characteristics figure 7. transfer characteristics figure 8. drain to source on resistance vs gate voltage and drain current figure 9. normalized drain to source on resistance vs junction temperature typical performance curves (continued) 110 10 2 10 3 v ds , drain to source voltage (v) 10 2 10 1 0.1 i d , drain current (a) t c = 25 o c t j = 150 o c single pulse operation in this area limited by r ds(on) 100 m s 10 m s 1ms 10ms dc 0 40 80 120 160 200 v ds , drain to source voltage (v) 15 12 9 6 3 0 i d , drain current (a) 80 m s pulse test v gs = 6v v gs = 4v v gs = 4.5v v gs = 5v v gs = 5.5v v gs = 10v 0246810 v ds , drain to source voltage (v) 15 12 9 6 3 0 i d , drain current (a) 80 m s pulse test v gs = 5v v gs = 4.5v v gs = 4v v gs = 5.5v v gs = 6v v gs = 10v 0246810 v gs , gate to source voltage (v) 100 10 1 0.1 i ds(on) , drain to source current (a) t j = 150 o c t j = 25 o c v ds 3 50v 80 m s pulse test 0 1020304050 5 4 3 2 1 0 i d , drain current (a) r ds(on) , drain to source 80 m s pulse test v gs = 20v v gs = 10v on resistance 3.0 2.4 1.8 1.2 0.6 0 -60 0 20 120 160 t j , junction temperature ( o c) normalized drain to source on resistance i d = 10a -40 -20 140 100 40 60 80 v gs = 10v irf340
5 figure 10. normalized drain to source breakdown voltage vs junction temperature figure 11. capacitance vs drain to source voltage figure 12. transconductance vs drain current figure 13. source to drain diode voltage figure 14. gate to source voltage vs gate charge typical performance curves (continued) 1.25 1.15 1.05 0.95 0.85 0.75 -60 0 20 120 160 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = 250 m a -40 -20 140 100 40 60 80 2500 2000 1500 1000 500 0 110 100 v ds , drain to source voltage (v) c, capacitance (pf) c iss c rss c oss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss ? c ds + c gs 1000 t j = 150 o c t j = 25 o c 048121620 i d , drain current (a) 15 12 9 6 3 0 g fs , transconductance (s) v ds 3 50v 80 m s pulse test 0 0.3 0.6 0.9 1.2 1.5 v sd , source to drain voltage (v) 100 10 1 0.1 i sd , source to drain current (a) t j = 150 o c t j = 25 o c 20 16 12 8 4 0 0 12243648 60 q g(tot) , total gate charge (nc) v gs , gate to source voltage (v) i d = 10a v ds = 320v v ds = 200v v ds = 80v irf340
6 test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms figure 17. switching time test circuit figure 18. resistive switching waveforms figure 19. gate charge test circuit figure 20. gate charge waveforms t p v gs 0.01 w l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs r l r g dut + - v dd t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 0.3 m f 12v battery 50k w v ds s dut d g i g(ref) 0 (isolated v ds 0.2 m f current regulator i d current sampling i g current sampling supply) resistor resistor same type as dut q g(tot) q gd q gs v ds 0 v gs v dd i g(ref) 0 irf340
7 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 irf340
|
